課程資訊
課程名稱
高等計算機結構
Advanced Computer Architecture 
開課學期
103-1 
授課對象
電機資訊學院  電子工程學研究所  
授課教師
楊佳玲 
課號
CSIE5059 
課程識別碼
922 U1470 
班次
 
學分
全/半年
半年 
必/選修
選修 
上課時間
星期二6,7,8(13:20~16:20) 
上課地點
資310 
備註
限修過計算機結構。
總人數上限:25人 
Ceiba 課程網頁
http://ceiba.ntu.edu.tw/1031CSIE5059_ 
課程簡介影片
 
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課程概述

Computer architecture has evolved — from a world of mainframes, minicomputers, and microprocessors, to a world dominated by microprocessors, and now into a world where microprocessors themselves are encompassing all the complexity of mainframe computers.
 

課程目標
This course focuses on advanced computer architecture design such as deep pipelining, techniques to exploit instruction level parallelism and thread level parallelism, and memory hierarchy management.
Students will acquire the skills of evaluating the performance of alternative design choices in system design.
 
課程要求
 
預期每週課後學習時數
 
Office Hours
 
指定閱讀
 
參考書目
Textbook & Reference Books:
(1) Computer Architecture: A Quantitative Approach. 5th Edition, John L.
Hennessy and David A. Patterson, Morgan, 20011
(2) Selected papers.
 
評量方式
(僅供參考)
   
課程進度
週次
日期
單元主題
第1週
9/16  Course Introduction 
第2週
9/23  Basics of Computer Architecture Design 
第3週
9/30  Memory Hierarchy: Cache Architecture 
第4週
10/07  (1) DRAM architecture
(2) Emerging NVM Technology 
第5週
10/14  (1) parallel-I-cache-coherency <br>
(2) Introduction to DRAM Memory System and the USIMM Simulation Framework
 
第6週
10/21  Parallel architecture (part II) : Thread-Level Parallelism/Multi-core Architecture 
第7週
10/28  [Cache Architecture] <br>
1.陳立展:Going Vertical in Memory Management: Handling Multiplicity by Multi-policy (ISCA 2014) <br>
2.王立:Locality-Aware Data Replication in the Last-Level Cache (ISCA 2014)<br>
3.張嘉麗: Improving Cache Performance by Exploiting Read-Write Disparity (HPCA 2014)<br>
4.賴洋: The Reuse Cache: Downsizing the Shared Last-Level Cache (Micro 2013)  
第8週
11/04  Dynamic Instrcution Scheduling/ Branch Predictor 
第9週
11/11  期中考週 
第10週
11/18  [DRAM architecture] <br>
1.謝元崵:Buffer Decoupling: A Case for Low-Latency DRAM Microarchitecture (ISCA 2014)<br>
2.葉志威:2. Half-DRAM: a High-bandwidth and Low-power DRAM Architecture from the Rethinking of Fine-grained Activation (ISCA 2014) <br>
3.唐皇:Improving DRAM Performance by Parallelizing Refreshes with Accesses <br>
4.葉丹:CREAM: A Concurrent-Refresh-Aware DRAM Memory System <br> 
第11週
11/25  (老師出國,並於12/18號補課)
 
第12週
12/02  Data-level Parallelislm /Warehouse Computing 
第13週
12/09  [GPU architecture] <br>
1.張志豪:Real-World Design and Evaluation of Compiler-Managed GPU Redundant Multithreading<br>
2.詹哲堯:Fine-grain Task Aggregation and Coordination on GPUs <br>
3.謝&#21647;宸:Enabling Preemptive Multiprogramming on GPUs<br>
4.薛立維:Eliminating Redundant Fragment Shader Executions on a Mobile GPU via Hardware Memoization <br>
5.A locality-Aware Memory Hierarchy for Energy-Efficient GPU Architecture 
第14週
12/16  [Data Center] <br>
1.江宗翰:A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services<br>
2.阮渥豪:Improving In-Memory Database Index Performance with Intel Transactional Synchronization Extensions<br>
3.何駿延:Exploiting Thermal Energy Storage to Reduce Data Center Capital and Operating Expenses <br>
4.李益昌:Implications of High Energy Proportional Servers on Cluster-wide Energy Proportionality  
第15週
12/23  3D ICs / Non-volatile Memory 
第16週
12/30  [NVM architecture] <br>
1.李翔昕:Memory Persistency (ISCA 2014) <br>
2.賴君濠:Adaptive Placement and Migration Policy for an STT-RAM-Based Hybrid Cache <br>
3.葉佳韋:Sprinkler: Maximizing Resource Utilization in Many-Chip Solid State Disks <br>
4.翁佩銀:Over-Clocked SSD: Safely Running Beyond Flash Memory Chip I/O Clock Specs  
第17週
1/06  Project Presentation 
第18週
1/13  期末考 
第14-2週
12/18  Project Discussion